Memory device and method of operation of a memory device

ABSTRACT

A method of operation of a memory device and a memory device having registers to store values representing a number of clock cycles to access and output data is provided in embodiments. Data is sensed from an array of memory cells using a plurality of sense amplifiers. A column address that identifies data sensed is latched using the plurality of sense amplifiers. The data is accessed, based on the column address, after a first number of clock cycles of a clock signal have elapsed after latching the column address. The first number of clock cycles is represented by a first value stored in a first register on the memory device. The data is output after a second number of clock cycles have elapsed after accessing the data from the array of memory cells. The second number of clock cycles is represented by a second value stored in a second register on the memory device. A column decoder driving a column select line based on the column address accesses the data.

FIELD OF THE INVENTION

The present invention relates generally to the control of dynamic randomaccess memory (DRAM) devices. More particularly, the present inventionrelates to the initialization and configuration of DRAM devices.

BACKGROUND OF THE INVENTION

Improvements in microprocessor designs have led to microprocessors witha high operating frequency. Current microprocessor designs may exceedoperating frequencies of 200 megahertz (MHz). However, the increase inoperating frequency typically has not led to fully acceptableperformance gains. One of the main components affecting performancegains is created by the microprocessor execution units idling duringdelays in external memory access. The delays in external memory accessare caused by the conventional design characteristics of static randomaccess memory (SRAM) cells, read only memory (ROM) cells, and dynamicrandom access memory (DRAM) cells.

To counteract the performance losses associated with external memoryaccess, Rambus Inc., of Mountain View, Calif. developed a high speedmultiplexed bus. FIG. 1 is a typical prior art system using the Rambushigh speed bus. In particular, the system 1000 comprises a masterdevice, or central processing unit (CPU) 10, coupled to slave devicesDRAM 20, SRAM 30, and ROM 40. Each device is coupled in parallel tosignal lines comprising DATA BUS, ADDR BUS, CLOCK, V_(REF), GND, andVDD. The DATA BUS and ADDR BUS signal lines comprise the data andaddress lines, respectively, used by CPU 10 to access data from theslave devices. The CLOCK, V_(REF), GND, and VDD signal lines comprisethe clock, voltage reference, ground, and power signals, respectively,shared between the multiple devices. Data is transferred by bus drivers(not shown) of each device driving signals onto the bus. The signals aretransmitted across the bus to a destination device.

To increase the speed of external memory accesses, the system 1000supports large data block transfers between the input/output (I/O) pinsof CPU 10 and a slave device. The system 1000 also includes designrequirements that constrain the length of the transmission bus, thepitch between the bus lines, and the capacitive loading on the buslines. Using these design requirements the system 1000 operates at ahigher data transfer rate than conventional systems. Accordingly, byincreasing the data transfer rate, the system 100 reduces the idle timein CPU 10.

The system 1000, however, does not provide enough bus bandwidth fordeveloping technologies. New technologies require data transfer ratesgreater than 500 megabits per second (Mb/s) per pin. Alternatively, newtechnologies require operation speeds of at least several hundred MHz.Operating at high frequencies accentuates the impact ofprocess-voltage-temperature (PVT) on signal timings and signal levels.The PVT variances result in numerous disadvantages that create hightransmission errors, or data loss, when operating the system 100 at afrequency of 400 MHz, for example.

A factor to be considered in high-speed bus operations is the precisecontrol and timing of the memory devices coupled to the bus. When thememory system is operated at low frequencies, communications between thememory controller and all of the memory devices on the bus are generallycompleted within the period of one clock cycle. However, onedisadvantage associated with operating the typical prior art memorysystem at a high frequency such as 400 MHz is that the system buspropagation delay between the memory controller and some memory devicesis longer than one clock cycle. This results in communications betweenthe memory controller and some memory devices taking longer than theperiod of one clock cycle to complete.

One method for dealing with this timing problem is to have the memorycontroller track the propagation delay times associated with each memorydevice so as to effectively manage the communications between eachdevice and the memory controller. This technique, however, heavily tasksthe memory controller and memory assets, thereby increasing the systemmemory requirements and introducing additional sources of delay due tothe additional processing requirements. A significant cost increase canresult from the use of this technique.

Numerous timing parameters are specified in multiple configurationregisters of the memory devices. Taken together, these timing parameterstypically specify communications between the memory controller and anynumber of memory devices. A problem with these prior art systems,however, is that the register fields of the typical memory devices arepreprogrammed with reset values that are supposed to guaranteefunctionality at the fastest specified clock rate of a particulardevice. However, optimal performance can only be achieved when some ofthe parameters are adjusted from their preset values. These adjustmentsare performed by the memory controller using register write requests;however, it has proven problematic for the prior art memory controllerto determine values at which these delays are set or to know values atwhich these delays are to be set. Typically, the only way for a memorycontroller to determine the reset value or to establish the optimumvalue is to query some form of device manufacturer register of thememory controller or the memory device for the vendor and memoryidentification, thereby allowing the memory controller to index througha look-up table of known optimal values. Unfortunately, this method doesnot allow for adjustments to compensate for process variations.Moreover, this method does not allow for dynamic adjustments to registervalues. Furthermore, this method fails for any memory devices introducedafter the memory control Basic Input/Output System was set.

Another disadvantage in operating typical prior art memory systems athigh frequencies is that correct functionality is guaranteed only whendevices having the correct speed device are placed on the channel.However, with the introduction of memory devices having a variety ofspeed grades, correct functionality is no longer guaranteed as there isno way for the prior art memory controller to detect that a slow part isplaced on a fast channel. The device may work most of the time, but failunder extreme operating or environmental conditions. This is a problemthat has plagued the computer industry since the first memory deviceswere binned according to access time. Thus, as the memory deviceconfiguration registers determine so much of the behavior of the memorydevice, the memory device initialization procedure is a vital element ofthe overall controller-memory interface.

Typical prior art memory systems take advantage of low power modesduring processor lulls in order to reduce the overall system powerconsumption. These low power modes are modes in which memory componentsor devices may be placed in lower frequency modes during periods ofinactivity or reduced activity. Another disadvantage of these prior artmemory systems is that a substantial delay in processing times may beincurred in waiting for these components to return to the higherfrequency mode.

SUMMARY AND OBJECTS OF THE INVENTION

It is therefore an object of the invention to provide memory deviceinitialization that includes levelizing of the system bus or channel,wherein levelizing comprises configuring each of the memory devicescoupled to the bus to respond to read commands from the correspondingmemory controller within a same number of clock cycles.

It is a further object of the invention to determine a minimum clockcycle offset between a read command and a subsequent write commandcommunicated to memory devices on a bus.

It is a further object of the invention to determine a minimum clockcycle offset between a write command and a subsequent read commandcommunicated to memory devices on a bus.

It is a further object of the invention to configure a power-down exitregister for use in bus clock acquisition upon returning a memory deviceto operation from a low-power state.

These and other objects of the invention are provided by a channelinitialization that levelizes the channel. In one embodiment, thelevelizing comprises determining the response time of each of a numberof DRAM devices coupled to a bus. Determining the response time for aDRAM device comprises writing logic ones to a memory location of theDRAM device using the bus. Subsequently, a read command is issued overthe bus, wherein the read command is addressed to the newly-writtenmemory location of the DRAM device. The memory controller then measuresthe elapsed time between the issuance of the read command and thereceipt of the logic ones from the DRAM device, and this elapsed time isthe response time of the DRAM device. The process is repeated for eachDRAM device coupled to the bus and the memory controller.

Following the determination of a response time for each DRAM device, andusing the longest response time, a delay is computed for each of theDRAM devices coupled to the bus so that the response time, in clockcycles, of each of the DRAM devices coupled to the bus equals thelongest response time. A delay is programmed in at least one register ofeach of the DRAM devices coupled to the bus by writing values to atleast one register of each of the DRAM devices.

Other objects, features, and advantages of the present invention will beapparent from the accompanying drawings and from the detaileddescription which follows below.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings, in which likereferences indicate similar elements, and in which:

FIG. 1 is a typical prior art system using the Rambus high speed bus.

FIG. 2 is a block diagram of a memory system comprising dynamic randomaccess memory (DRAM) devices in one embodiment.

FIG. 3 is a block diagram of a DRAM device of one embodiment.

FIG. 4 is a block diagram of a 64/72-Mbit DRAM device of one embodiment.

FIG. 5 is a memory core of one embodiment.

FIG. 6 is the arrangement of the storage cells in the storage array ofone embodiment.

FIG. 7 is a DRAM storage cell of one embodiment.

FIG. 8 is the DRAM row timing signal waveforms for the row operation ofone embodiment.

FIG. 9 shows the minimum time between precharge operations and senseoperations to different banks of memory in one embodiment.

FIG. 10 is the circuitry that supports a column operation in a memorycore of one embodiment.

FIG. 11 is the column read timing for a read operation of oneembodiment.

FIG. 12 is the column write timing for a write operation of oneembodiment.

FIG. 13 is a high-level flowchart of the initialization of the DRAMdevices of one embodiment.

FIG. 14 is a detailed flowchart of the initialization of the DRAMdevices of one embodiment.

FIG. 15 is a detailed flowchart of the levelization of the DRAM devicesof one embodiment.

FIG. 16 illustrates the interaction between a Read secondary controlpacket (SCP) and a subsequent Write SCP of one embodiment.

FIG. 17 illustrates the interaction between a Write SCP and a subsequentRead SCP of one embodiment.

FIG. 18 is a flowchart of the procedure for setting the device sequenceaddresses in DRAM devices of one embodiment.

DETAILED DESCRIPTION

A method and apparatus for initializing dynamic random access memory(DRAM) devices is provided wherein a channel is levelized by determiningthe response time of each of a number of DRAM devices coupled to a bus.Determining the response time for a DRAM device comprises writing logicones to a memory location of the DRAM device using the bus.Subsequently, a read command is issued over the bus, wherein the readcommand is addressed to the newly-written memory location of the DRAMdevice. The memory controller then measures the elapsed time between theissuance of the read command and the receipt of the logic ones from theDRAM device, and this elapsed time is the response time of the DRAMdevice. Following the determination of a response time for each DRAMdevice, and using the longest response time, a delay is computed foreach of the DRAM devices coupled to the bus so that the response time,in clock cycles, of each of the DRAM devices coupled to the bus equalsthe longest response time. A delay is programmed in at least oneregister of each of the DRAM devices coupled to the bus by writingvalues to at least one register of each of the DRAM devices.

FIG. 2 is a block diagram of a memory system 100 comprising DRAM devicesin one embodiment. A memory controller 102 is coupled to four DRAMdevices 110-116 using two different sets of connections 120 and 122, butthe embodiment is not so limited. One set of connections forms a bus 120or channel over which information is passed between the memorycontroller 102 and all DRAM devices 110-116. Another set of connectionsforms an auxiliary channel 122 over which an SIO signal is communicated.In one embodiment, this low-speed serial chain 122 loops through allDRAM devices 110-116 on the channel using the complementary metal-oxidesemiconductor (CMOS) input and output pins SIO0 and SIO1, but theembodiment is not so limited. The auxiliary channel 122, while beingused to initialize the DRAM devices 110-116 and control DRAM deviceregister values, makes it possible to restrict the DRAM devices thatreceive information passed along the auxiliary channel 122.

The memory controller 102 of one embodiment comprises a levelizingcircuit 130, a first offset circuit 150, a second offset circuit 152,and a delay lock loop (DLL) configuration circuit 154 coupled to themain channel 120 through a main channel interface 140. The levelizingcircuit 130 and the DLL configuration circuit 154 are coupled to theauxiliary channel through the auxiliary channel interface 142.

The levelizing circuit 130 comprises a timing circuit 132, an evaluationcircuit 134, a delay circuit 136, and a programming circuit 138. Inoperation, as discussed herein, the levelizing circuit 130 levelizes aread domain of the DRAM devices 110-116 by configuring each of the DRAMdevices 110-116 to respond to read commands from the memory controller102 in the same amount of time, but the embodiment is not so limited.The timing circuit 132 is configured to determine the response time ofeach of the DRAM devices 110-116 using information communicated over themain channel 120. The evaluation circuit 134 is configured to determinethe longest response time of the response times determined by the timingcircuit 132. The delay circuit 136 is configured to compute a delay foreach of the DRAM devices 110-116 so that the response time of each ofthe DRAM devices 110-116 equals the longest response time. Theprogramming circuit 138 is configured to program the delay in each ofthe DRAM devices 110-116 by writing values to at least one register ofeach of the DRAM devices 110-116 using the auxiliary channel.

The first offset circuit 150 is configured to determine a minimum clockcycle offset between a read command and a subsequent write commandcommunicated to the DRAM devices 110-116 over the main channel 120. Thesecond offset circuit 152 is configured to determine a minimum clockcycle offset between a write command and a subsequent read commandcommunicated to the DRAM devices 110-116 over the main channel 120. TheDLL configuration circuit 154 is configured to configure at least onepower-down exit register in the DRAM devices 110-116 for DLLacquisition.

The various components of the memory controller 102 may be hosted inhardware, firmware, software, or some combination of hardware, firmware,and software, but the embodiment is not so limited. In one embodiment,the memory controller 102 may use a digital processor using algorithmsand data stored in memory devices to implement the functions of thelevelizing circuit 130, the first offset circuit 150, the second offsetcircuit 152, the DLL configuration circuit 154, and the componentsthereof, but the embodiment is not so limited.

Two additional signals 124 and 126 are used in conjunction with the SIOsignal from the memory controller. The first additional signal is theCMD signal 124 which indicates a new SIO operation is being transmittedon the auxiliary channel. As the CMD signal indicates that a new SIOoperation is being transmitted, the CMD signal is said to frame SIOoperations. The second additional signal is the SCK signal 126, which isthe clock signal transmitted with the data on the auxiliary channel andthe CMD signal.

As previously discussed, each DRAM device has two CMOS input pins SIO0(with reference to FIG. 4, SIN) and CLIN and two CMOS output pins SIO1(with reference to FIG. 4, SOUT) and CLOUT. These pins provide serialaccess to a set of control registers in each DRAM device. These controlregisters provide configuration information to the controller during theinitialization process, and allow an application to select theappropriate operating mode of the DRAM device. The CLIN is afree-running CMOS clock driven by the controller to the first DRAMdevice. The SIN is a CMOS serial input. In one embodiment, both inputsare low-true, so the high signal voltage is a logic zero, but theembodiment is not so limited. In normal operation, the two inputs arerepeated on the CLOUT and SOUT outputs, which connect to the inputs ofthe next DRAM device on the bus. Write and read transactions to controlregisters are each composed of four packets, wherein each packetcomprises 32 bits.

In operation, the DRAM devices 110-116 are first configured and then putinto service. In one embodiment, the process of configuring the DRAMdevices 110-116 comprises initialization operations. The initializationoperations comprise setting register values used to control the timingof operations that write data to and read data from the DRAM devices110-116. The initialization operations are performed over the auxiliarychannel 122, while the operations comprising writing data to and readingdata from the DRAM devices are performed over the bus 120. Therefore,initialization commands may be carried using the SIO pins of each DRAMdevice 110-116, while commands for data to be written to and read fromeach DRAM device 110-116 are carried over the main channel connectionsof the DRAM devices 110-116. In one embodiment, the main channelconnections comprise RSL pins, but the embodiment is not so limited.

Furthermore, the auxiliary channel 122 and the SIO pins are capable ofbeing used to dynamically configure at least one register in the DRAMdevices during memory access operations over the bus. The main channelconnections that couple the DRAM devices 110-116 to the bus 120 arelogically separated into two groups, one for transmitting a class ofcommands called Primary Control Packets (PCPs), and one for transmittinga class of commands called Secondary Control packets (SCPs). The PCPsare used to communicate Row Address (RAS) commands that perform thefirst half of a memory access, but the embodiment is not so limited. TheSCPs are used to communicate Column Address (CAS) commands that performthe second half of a memory access, but the embodiment is not solimited.

Each DRAM device has an input and an output data pin SIO0 and SIO1 overwhich the initialization information is passed. A configurable register,or SIO repeater register, in each DRAM device allows informationpresented on the SIO0 pin of a DRAM device to be placed or repeated onthe SIO1 pin of the DRAM device so that information can be propagated toDRAM devices that are further down the serial chain. The DRAM deviceshave two unique identifiers: one identifier is used for SIO, orinitialization, operations and is hence associated with the auxiliarychannel over which initialization commands are communicated to the DRAMdevice; and, one identifier is used for bus operations and is henceassociated with the bus over which read and write operations areperformed. When an SIO operation is performed, the operation has anassociated SIO identification (ID). When the repeater register is setappropriately, the SIO operations are propagated down the SIO serialchain to all devices on the serial chain, wherein the device having anSIO ID matching that of the SIO operation takes appropriate action. Whena bus operation is performed, the operation has an associated memoryaddress or ID that is used the particular DRAM device; therefore, in oneembodiment, there is one DRAM device ID used per bus for each of twobuses, but the embodiment is not so limited.

In the case where an SIO register read is performed in which the memorycontroller wishes to read the value in a DRAM device register, the valueof the register must be passed back to the memory controller. As the SIOserial chain of one embodiment does not wrap back around from the lastDRAM device in the serial chain to the memory controller, this data mustbe passed back by reversing the directionality of the SIO0 and SIO1 pinsof each device. Therefore, when passing data back to the memorycontroller from a DRAM device using the auxiliary channel of oneembodiment, SIO1 becomes an input pin and SIO0 becomes an output pin.

In application, DRAM devices can be grouped together onto in-line memorymodules. There is no set number of devices that must be on a module,subject to the maximum number of devices allowed on the channel In thisapplication, each in-line memory module may contain a special area ofstorage that allows for a process known as Serial Presence Detect (SPD).Serial Presence Detect information includes the number of DRAM deviceson the module, as well as some of the timing and architecturalcharacteristics of the DRAM devices on the module. During the process ofinitialization, the memory controller must read SPD information, ifavailable, in order to decide how best to handle and process memoryrequests. However, SPD information is accessed through a different setof wires in one embodiment, so it is not accessed using the main channelconnections or the auxiliary channel, but the embodiment is not solimited.

In one embodiment, the DRAM devices may be configured to operate at twodifferent frequencies during operation while the initializationoperations are conducted at a different frequency. Therefore, theinitialization operations are performed at a frequency approximatelyequal to 1 megahertz (MHz) using a first protocol, while the memoryaccess operations may be performed at a frequency approximately equal toeither 400 MHz or 50 MHz using a second protocol, but the embodiment isnot so limited. While the DRAM devices of a system are operating at thesame frequency, a transition may be made to move the DRAM devicesbetween a faster and a slower frequency. The clock that drivesoperations at the faster frequency is called the fast clock, and theclock that drives operation at the slower frequency is called the slowclock. When operating using the fast clock, a different set of registersmay be used by the DRAM devices for some types of operations than whenthe DRAM devices are operating using the slow clock.

FIG. 3 is a block diagram of a DRAM device 110 of one embodiment.

The DRAM device comprises, but is not limited to, delay lock loop (DLL)circuitry, an interface 204 and 206, control registers 210, power modecircuitry 212, and core memory 208. The interface 204 and 206 comprisesa main channel interface 204 and a SIO command interface 206. The mainchannel interface 204 couples the DRAM device 110 to the bus 120 andpasses information between the core memory 208 of the DRAM device 110and the bus 120. The SIO command interface is coupled to the SIO0 andSIO1 pins of the DRAM device and couples the DRAM device to theauxiliary channel over which the SIO signals are passed. The SIO commandinterface 206 is coupled to communicate information to and from thecontrol registers 210 of the DRAM device 110. The control registers 210are coupled to provide register information to the power mode circuitry212. The DLL circuitry senses and tracks the edges of the high-speed busclock signals and, in accordance therewith, determines the optimalplacement of information from the DRAM device memory core on the bus120. The bus clock may operate at a speed of 400 megahertz (MHz) or aspeed of 50 MHz, but the embodiment is not so limited.

The DRAM devices of one embodiment may operate in one or more low powermodes in order to reduce the power consumption of the memory device.When the DRAM devices transition from a low-power mode to a full-powermode, there may be a period of time in which the DRAM devices should notbe read from or written to because the device is not electrically readyto accept such transactions. To reduce the latency associated with thetransition period, the DLL circuit uses two sets of biasing information,coarse and fine, so as to provide for limited functionality of the DRAMdevices during the transition period. During a first period of timeimmediately following a start of the transition out of a low-power mode,the coarse biasing information is used to allow the DLL to providelimited acquisition of the bus clock signal. Following this first periodof time, when the full-power mode is reached, the fine biasinginformation is used to allow the DLL to fully synchronize with the busclock signal.

Initialization of the DRAM devices comprises configuring at least onepower-down exit register of each DRAM device for use in delay lock loop(DLL) acquisition. This configuration is performed using the SIO signalcommunicated over the auxiliary channel coupled among the DRAM devices.Configuration of the power-down exit registers comprises storing a setof coarse biasing information of the DLL in a first register of thecorresponding DRAM device and storing a set of fine biasing informationof the DLL in a second register of the corresponding DRAM device. TheDLL uses the biasing information from the first and the secondregisters, upon recovery from a low-power mode, to re-establishsynchronization with the bus clock signal or pulse.

FIG. 4 is a block diagram of a 64/72-Mbit DRAM device of one embodiment.This DRAM device comprises two major blocks: a core block comprisingbanks and sense amps similar to those found in other types of DRAM, andan interface block which permits an external controller to access thiscore at up to 1.6 gigabytes per second. The 8 Mbyte core memory of theDRAM device is divided into sixteen 0.5 Mbyte banks, each organized as512 rows, with each row comprising 64 dualocts, and each dualoctcontaining 16 bytes. A dualoct is the smallest unit of data typicallyaddressed in this DRAM device, but the embodiment is not so limited. Inone embodiment, each DRAM device contains 17 sense amp arrays, but theembodiment is not so limited. Each sense amp consists of 512 bytes offast storage and can hold one-half of one row of one bank of the DRAMdevice. The sense amp may hold any of the 512 half-rows of an associatedbank. A 3-pin row-access-control bus (ROW) is used to manage thetransfer of data between the banks and the sense amps of the DRAMdevice. These pins are de-multiplexed into a 24-bit ROWA (row-activate)or ROWR (row-operation) instruction.

The SIO0 or SIN, SIO1 or SOUT, CLIN, and CLOUT pins are used to writeand read a block of control registers. These registers supply the DRAMdevice configuration information to the memory controller and theyselect the operating modes of the device. The 9-bit REFR value is usedfor tracking the last refreshed row. Most importantly, the 5-bit DEVIDspecifies the device address of the DRAM device on the channel.

The clock-to-master (CTM and CTMN) signals become the transmit clock(TCLK) which is the internal clock used to transmit read data. Theclock-from-master (CFM and CFMN) signals become the receive clock (RCLK)which is the internal clock signal used to receive write data an-d toreceive the ROW and COL buses.

These two 9-bit buses carry read and write data across the main channel.They are multiplexed/de-multiplexed from/to two 72-bit buses running atone-eighth the data frequency inside the DRAM device. A 5-pincolumn-access-control bus (COL) is to manage the transfer of databetween the DQA/DQB buses and the sense amps of the DRAM device.

FIG. 5 is a memory core of one embodiment. FIG. 6 is the arrangement ofthe storage cells 6150 in the storage array 6245 of one embodiment.Storage array 5145, comprising the actual storage cells 6250, is shownwith various other circuit blocks necessary to store and retrieve datafrom the storage array 5145, but the embodiment is not so limited.Support circuitry comprises a row decoder and control block 5175, acolumn decoder and control block 5185, sense amplifiers 5135, and columnamplifiers 5165. The row decoder and control 5175 receives row controland address signals PRECH 5162, PCHBANK 5152, SENSE 5142, SNSBANKADDR5132, and SNSROWADDR 5122. The row decoder and control 5175 driveswordline signals 5170 into the storage array 5145 and drives row controlsignals 5115 into the sense amplifiers 5135. The column decoder 5185receives the column address and control signals 5140. The column decoder5185 drives the column select lines 5125 to the sense amplifiers 5135and drives the column control signals 5190 to the column amplifiers5165. Sense amplifiers 5135 receive the column select lines 5125, therow control signals 5115, and the array data 5160 and 5150 from thestorage array 5145. Column amplifiers 5165 receive the sense amplifierdata 5130 and the column control signals 5190 and drive the sensed data5110 to circuits outside the memory core or data to be written into thesense amplifiers 5135.

Lines 6210 entering the storage array 6245 correspond to lines 5170 inthe memory core 5100 and are the wordlines 6220 used for selecting a rowof storage cells. Lines 6240 correspond to lines 5160 in the memory core5100 and are the bit lines used for receiving data from one of thecolumns 6230 of a selected row of cells.

FIG. 7 is a DRAM storage cell 7350 of one embodiment. The DRAM storagecell 7350 comprises an access transistor 7320 coupled to the wordline7330 and a storage capacitor 7310 on which data is stored as charge. Thecharge on the storage capacitor 7310 is coupled through the accesstransistor 7320 to the bitline 7340 when the wordline 7330 is activated.When access transistor 7320 couples the stored charge to the bit line,the charge on the storage capacitor 7310 is reduced; the charge on thestorage capacitor 7310 should be restored if data is not to be lost.

FIG. 8 is the DRAM row timing signal waveforms for the row operation ofone embodiment. In performing a row access on the memory core,pre-charge signal PRECH 8462 initiates a cycle upon a certain bankPCHBANK 8452 that prepares the bit lines to receive the stored charge,wherein the cycle time is no shorter than parameter tRC 8410. Sensesignal 8442 initiates a cycle upon a particular bank SNSBANKADDR 8432and row SNSROWADDR 8422 to couple the stored charge to the senseamplifiers. Upon receiving the sense signal 8442, a wordline 8420 isactivated and a bit line 8430 responds to the stored charge beingcoupled to it. After a time tRCD 8450, a column access of data in thesense amplifiers may be performed. The sensed data in the senseamplifiers is restored onto the storage cells and another precharge,lasting a time tRP 8425 after tRAS,min 8435, is allowed that againprepares the bit lines for another cycle. It is noted that DRAM timingparameters can vary widely across various memory core designs,manufacturing processes, supply voltage, operating temperature, andprocess generations. In one embodiment, an access from a core using aprecharge before a sense operation takes about 45 nanoseconds (ns) andthe cycle takes about 80 ns, wherein the difference of 35 ns is the timeto restore the charge on the accessed storage cells.

With reference to FIG. 5, it is noted that multiple banks are shown inthe memory core 5100, but the embodiment is not so limited. Inparticular, bank 5155 has a separate storage array 5145 and set of senseamplifiers 5135. Furthermore, bank 5156 has a separate storage array andset of sense amplifiers. Banks 5155 and 5156 may be independent in thesense that one bank may be carrying out a precharge operation, while theother is performing a sense operation, given sufficient control from rowdecoder and control 5175. Thus, having multiple banks permits concurrentoperation between the banks.

FIG. 9 shows the minimum time between precharge operations and senseoperations to different banks of memory in one embodiment. Parameter tPP9510 determines the minimum time between precharge operations todifferent banks in the same device. Parameter tSS 9520 determines theminimum time between sense operations to different banks in the samedevice. In one embodiment, parameters tPP and tSS are on the order of 10to 20 ns which is less than the access time from a single bank andsmaller than the cycle parameter tRC which applies to a single bank.

Multiple banks may be coupled in some memory cores to other banks,wherein the other banks are adjacent banks, but the embodiment is not solimited. In particular, when a first bank shares a portion of the senseamplifiers with a second bank, the first bank becomes dependent upon thesecond bank in that the two banks cannot typically be operatedconcurrently. However, the dependent banks allow a large number of banksin a core without the penalty that might be encountered when using alarge number of sense amplifier arrays, many of which may be operatedwithout constraint. Precharging the banks may become more complexbecause a precharge may be required for each bank, resulting in a largenumber of precharge operations. However, in one embodiment, the memorycore can convert a precharge operation of a first bank into a prechargeof the first bank and the banks dependent upon the first bank. Inanother embodiment, the memory device circuitry can convert a bankprecharge into multiple operations.

FIG. 10 is the circuitry that supports a column operation in a memorycore of one embodiment. Column decoder 10685 receives the column controlsignals and the column address signals 10640 and drives the columnselect lines 10625 into the sense amplifiers 10635 to select some or allof the outputs from the sense amplifiers 10635. Sense amplifiers 10635receive the bit lines 10660 from the storage array 10645, the columnselect lines 10625 from the column decoder and controller, and theselected amplifiers drive the column I/O lines 10630 into the columnamplifiers 10665. Column amplifiers 10665 receive one of the columncontrol signals 10646 from the column control 10640, the write data10622, and the write mask 10624, but the embodiment is not so limited.Column amplifiers 10665 drive read data 10620 to circuitry external tothe memory core. Typically, the column I/O lines 10630 are differentialand are sensed by differential column amplifiers in order to speedcolumn access time, but the embodiment is not so limited. In theembodiment of FIG. 10, bidirectional column I/O lines 10630 carry thewrite data and read data. In an alternate embodiment, column I/O 10630is unidirectional resulting in separate pathways for write data and readdata into and out of the sense amplifiers from the column amplifiers. Inanother alternate embodiment, I/O WRITEDATA 10622 and READDATA 10620 areseparate buses that allow for some concurrency between the senseamplifiers and the column amplifiers, but the embodiment is not solimited. In an alternate embodiment, the data I/O lines arebidirectional, wherein the WRITEDATA 10622 and READDATA 10620 sharethe-same bus. The number of lines in the WRITEDATA bus 10622 and theREADDATA bus 10620 determine the amount of data, or column quantum, foreach column access from the core. Typical sizes range from 64 bits to256 bits for each bus, but the embodiment is not so limited.

FIG. 11 is the column read timing for a read operation of oneembodiment. Read operations cycle two signals, COLLAT 11744 and COLCYC11746, with minimum cycle time tPC 11750. Typically, the column cycletime tPC is about 10 ns, but the embodiment is not so limited. Thesignal COLLAT 11744 starts slightly ahead of COLCYC 11746 by parametertCLS 11788 and latches the column address 11740 in the column decoder.This permits the signal COLADDR to be introduced into the column decoderfor the next cycle while the data is available on the previous cycle andhelps to remove the delay of the column decoder from the access path.The signal COLLAT 11744 follows the SENSE signal with a delay of tCSH.In one embodiment, the signal COLADDR uses set and hold times tASC andtCAH with respect to the COLLAT signal. The signal COLCYC 11746 cyclesat the same minimum rate tPC as the COLLAT signal. The availability ofread data is a delay tDAC 11782 from the leading edge of the signalCOLCYC. The tCAS 11780 is the period of time that signal COLCYC is inthe high state, and tCP 11760 is the period of time that signal COLCYCis in the low state.

FIG. 12 is the column write timing for a write operation of oneembodiment. The column write cycle is similar to the read cycle for thesignals COLCYC 12846 and COLLAT 12844; the major difference is that theWRITEDATA 12834 should be setup by an amount tDS 12852 prior to theCOLCYC signal. Furthermore the WRITEDATA must be held until an mount tDH12854 after the time tCAS 12880 expires on the COLCYC signal 12846. TheWMASK 12832 input has approximately the same timing as the WRITEDATAsignal and is governed by parameters tWES 12836 and tWEH 12838. In oneembodiment, a column cycle can occur rather quickly compared to a rowcycle. Typical column cycle times are about 10 ns as compared to the 80ns for a row cycle, but the embodiment is not so limited. It may bedesirable to maintain a sequence of column quantum accesses at thecolumn cycle rate, under a variety of application reference streams, butthe embodiment is not so limited.

A register transaction to a DRAM device begins with the transmission ofa Control Register Request packet; this packet is framed with two startbits. This packet contains the Control Register Opcode field, whichselects the transaction type. A Control Register Sequence address fieldselects one of the DRAM devices on the serial chain. If a ControlRegister Broadcast field is set, then all DRAM devices coupled to theserial chain are selected. A Control Register Address packet follows theControl Register Request packet and contains a 12-bit address forselecting a control register.

A write transaction comprises a Control Register Data packet thatcontains 16 bits of data that is written into the selected controlregister. A Control Register Interval packet follows the ControlRegister Data packet, providing some delay for any side-effects to takeplace.

A read transaction comprises a Control Register Interval packet followedby a Control Register Data packet. In this manner, a delay is providedduring which the selected DRAM device accesses the control register.

In one embodiment, the input and output data pins SIO0 and SIO1 of eachDRAM device are dynamically configurable in response to an SIO signalcommunicated over the serial chain. With reference to FIG. 3, the SIO0and SIO1 pins are coupled to the SIO command interface 206 through anSIO pin configuration circuit 299. Configuring the SIO pins comprisesconfiguring both the SIO0 and the SIO1 pins as input pins. The SIOsignal from the memory controller will arrive at the DRAM device on theinput pin. The pin configuration circuit 299 detects the logical highvalue of the arriving SIO signal on the input pin. Upon detection of thelogical high value, the SIO pin configuration circuit enables the outputdrivers on the pin that did not receive a signal, wherein the pin thatdid not receive the signal is thereby configured as the output pin. Thisprocess continues sequentially down the chain of DRAM devices as the SIOsignal is passed among the DRAM devices.

Initialization refers to the process that a memory controller must gothrough after power is applied to the memory system or the memory systemis reset. The controller prepares a DRAM subsystem comprising DRAMdevices for bus operations by using a sequence of control registertransactions on the serial CMOS bus, or auxiliary channel. FIG. 13 is ahigh-level flowchart of the initialization of the DRAM devices of oneembodiment. FIG. 14 is a detailed flowchart of the initialization of theDRAM devices of one embodiment.

In one embodiment, the purpose of the initialization sequence is toprepare the DRAM devices for operation, and to gather information aboutthe DRAM devices that enables a memory controller to use the DRAMdevices efficiently. With reference to FIG. 13, the sequence ofoperations involved in initializing the DRAM devices comprise thefollowing steps apply power 1302; read/write DRAM device information toinitialize the DRAM devices, and use information about the DRAM devicesto configure the memory controller to achieve desired performance levels1304; and begin service operations 1306. This sequence of operationsshows an ordering of the events that should occur before theinitialization process completes. With reference to FIG. 14, the blockrepresenting step 1304 comprises steps 1402 through 1434.

With reference to FIG. 14, operation begins at step 1401, at which poweris applied to the memory system. Following the application of power,there is an amount of time that should elapse before the DRAM devicescan have data written to aid read from the core memory. Furthermore, aperiod of time should elapse before initialization commands can bereceived and interpreted by the DRAM devices on the SIO pins.

At step 1402, a timer is started for DRAM device core operations. Atthis step a timer is started that indicates how much time should beallowed to elapse before data can be written to and read from the DRAMdevices using the bus, or main channel, and the DRAM device mainconnection pins. During the course of initialization it may be desirableto write data to the DRAM devices and read it back, and this should notbe attempted before the time period indicated by the core operationstimer. Core operations should not be attempted before the coreoperations timer elapses because the core may not be ready electricallyto perform read and write operations. The channel clock, or CTM/CFMclock is started, at step 1403. All information passed along the bus, ormain channel, between the main connection pins of the memory controllerand the DRAM devices is transmitted using this clock. At step 1404, atimer is set to track the amount of time allowed for the channel clockto settle before information passed along the main channel should besent using the channel clock.

Operation continues at step 1405, at which the channel or bus populationis checked or determined. At this step, the number of DRAM devicescoupled to the bus is determined. At least one DRAM device should becoupled to the bus, and no more than the maximum number of DRAM devicesallowed by the protocol and physical characteristics of the bus shouldbe coupled to the bus. In one embodiment, in order to determine thenumber of DRAM devices coupled to the channel, configuration informationstored in the SPDs indicates the number of DRAM devices on each module,and the sum total determines how many are coupled to the channel. If themaximum number of DRAM devices allowed on the main channel is exceeded,an error is reported. One embodiment allows for as many as 36 DRAMdevices to be coupled to the main channel, but the embodiment is not solimited.

It is noted that one embodiment discussed herein uses SPDs. However, theembodiment is not limited to the use of SPDs. In embodiments which donot use SPDs, some information referred to as being stored by the SPDsis stored in registers of the DRAM devices. Other information would haveto be known based on manufacturer information or part numberinformation.

The clock frequency is checked, at step 1406. In an embodiment in whichthe system uses fixed fast and slow clock frequencies, this step is usedto check that the devices on the channel can handle the correspondingclock periods. In performing this step, four fields are read from eachSPD, wherein two fields pertain to the fast clock and two fields pertainto the slow clock. The two fields pertaining to the fast clock are thetCYC, Min Fast register field and the tCYC, Max Fast register field. Ifthe Fast Clock generator period is less than the value of tCYC, Min Fastread from an SPD, this indicates that the clock generator does notproduce a clock with high enough frequency that can be used by the DRAMdevices associated with that SPD. Likewise, if the fast clock generatorperiod is greater than the value of tCYC, Max read from an SPD, thenthis indicates that the clock generator produces a clock with afrequency higher than acceptable to the DRAM devices associated withthat SPD. In this case, an error is reported. Furthermore, thecorresponding values in the tCYC, Min Slow and tCYC, Max Slow registerfields are read and compared against the slow clock period to ensurethat the slow clock period of the memory controller fits in this range.

At step 1407, SPD information is read to determine what values will bewritten into register fields in each DRAM device so that the DRAM devicewill function properly and efficiently. The SPD information is stored inunits of time, but the memory controller and DRAM devices manipulatethis information in terms of clock cycles. For each SPD associated withthe channel, the values read comprise: tRCD, tRP, tRAS, tSS, and tPP.For each of these values, which are in units of time, the times areconverted to fast clock cycles and slow dock cycles. For example, thevalue of tRCD, in units of time, is converted to units of clock cyclesso that a memory controller can use this information in a form which itis accustomed to manipulating. To convert this timing to clock cycles,the value of tRCD is divided by the clock period. The ceiling functiontakes any remaining fractional number of cycles and rounds up to thenext whole integer cycle, as whole cycles are the smallest unit of timethat a controller can use. The formulas for converting to fast clockcycles comprise:cycRCDspd=ceiling(tRCD/{Fast Clock period})cycRPspd=ceiling(tRP/{Fast Clock period})cycRASspd=ceiling(tRAS/{Fast Clock period})cycSSspd=ceiling(tSS/{Fast Clock period})cycPPspd=ceiling(tPP/{Fast Clock period})

Moreover, the overall system values for each of these parameters aredetermined. The system value for each parameter is simply the largestSPD value for each of the above calculated values. The memory controlleris then configured with these system values. For the slow clock, thesame formulas above are used, except that the value of the slow clockperiod is used as the denominator instead of the fast clock period.

The CMD framing is initialized, at step 1408. This initialization isperformed by setting CMD to 0 for two initialization clock cycles.

Operation continues at step 1409, at which the DRAM devices areinitialized for subsequent SIO operations. In one embodiment, therepeater register of each DRAM is set to logical 1 to indicate that anyincoming data read on the SIO0 pin should be repeated on the output SIO1pin. In this step, a number of other registers are also set to theirdefined reset value. Furthermore, internal circuitry is initialized toallow register reads/writes. Upon completion, an SIO reset command issent to each DRAM device.

At step 1410, uninitialized DRAM device test registers are set tological 0. This is accomplished by performing a broadcast write with thevalue of 0 on the SIO channel for each test register field. Thebroadcast write is a single command that writes the same value to allDRAM devices coupled to the auxiliary channel, but the embodiment is notso limited. At step 1411, registers are set that are indicative of themethod for performing device addressing upon exit of low power states.The DLL period register is configured, at step 1412.

Prior to this point in the initialization, communications between theDRAM devices and the memory controller have been performed throughbroadcast operations in one embodiment. At step 1413, each DRAM deviceis assigned a unique ID to allow individual devices to be addressed.Furthermore, other registers are configured at this step. Moreover, FIG.18 is a flowchart of the procedure for setting the device sequenceaddresses in DRAM devices of one embodiment. To begin, a broadcast writeoperation is performed to: set the SIO repeater register value to 0, inorder to break the DRAM device serial chain; set the Device SequenceAddress (DSA), or the unique ID used by a DRAM device during SIOoperations, to 31; and, set the Powerdown Self Refresh field to 0, inorder to prevent self-refresh before the memory core is ready. In oneembodiment, these operations may be performed in a single broadcastwrite because they are all fields or different dedicated bits in thesame register, and registers may be written in one operation.

Following the broadcast write, a counter that indicates the SIO D forthe next device, or seq-id, is set to 0. The sequence addresses, orunique SIO IDs, are then set for each DRAM device. For each DRAM device,the following sequence is performed: an SIO operation is performed todevice 31, thereby resetting the Device Sequence Address of device 31 tothe value of seq-id; the SIO repeater register is set to 1; the PowerExit Select is set to match whatever policy and physical configurationis being used by the memory controller; the Powerdown Self Refresh fieldis set to 0; the Reset Power Mode field is set to the proper value toindicate whether fast clock or slow clock will be used for Set/ClearReset; and, seq-id is incremented so that the next DRAM device receivesthe next value as its SIO ID.

Operation continues at step 1414, at which a determination is made ofthe assignment of DRAM devices to address space based on memorycontroller and system policy. For each SPD, information comprising thefollowing is read: Bank Bits register; Row Bits registers; Column Bitsregister; Byte Width register; and Dependent Banks register. The BankBits register indicates how many bits, or binary digits, are used touniquely identify one bank in the DRAM. For example, if the device hastwo banks, then 1 bit is used, while if the device has four banks, 2bits are used. The Row Bits register indicates how many bits are used touniquely identify one row in a bank of the DRAM. The Column Bitsregister indicates how many bits are used to uniquely identify one16-byte quantity, the minimum unit of information that can be read froma DRAM, from a row of a bank in the DRAM. The Byte Width registerindicates whether the data portion of the channel transmits 16 bits ofinformation per clock edge or 18 bits of information per clock edge. TheDependent Banks register indicates whether the DRAM uses dependent orindependent banks in its core implementation. After the controllerestablishes the address configuration, each DRAM device is given anappropriate Device Address.

At step 1415, the Nap Exit registers are configured. The Nap mode is alow power mode in which the DRAM devices may be operated. The tNAP0 andtNAP1 times are the times for the first and second Nap exit phases. Whena DRAM device exits the Nap state, the time before the DRAM device canbe addressed with commands is based on tNAP1. The tNAP0 describes theperiod of time before the delay lock loop (DLL) of the DRAM devicereaches a predetermined state. For each SPD associated with the channel,the values of tNAP0 and tNAP1 are read and converted to cycles accordingto the formulas:cycNAP0spd=ceiling(tNAP 0/{powermode SCK period})cycNAP1spd=ceiling(tNAP 1/{powermode SCK period})cycNAPspd=cycNAP0+cycNAP1The system value for NAP, called cycNAPsys, is set as the greatest valueof cycNAPspd for all SPDs. Then, for each DRAM device, the Nap ExitPhase 0 register is set to the value of cycNAP0spd derived above fromthe associated SPD. For each DRAM device, the Nap Exit Phase 1 registeris set to the value of (cycNAPsys−cycNAP0spd).

Operation continues at step 1416, at which operational column registersare set to maximum performance with consistent behavior for all DRAMdevices. For each SPD, the values of tCLS and tCAS are read andconverted to cycles according to the formulas:cycCLSspd=ceiling(tCLS/{Fast Clock period})cycCASspd=ceiling(tCAS/{Fast Clock period})The values for cycCLSsys and cycCASsys are computed as the greatest ofeach of the individual cycCLSspd and cycCASspd values from the SPDcalculations. Corresponding registers in the DRAM devices are writtenduring the next step. Based on cycCLSsys, the offset for write datapackets is determined for use by the memory controller. Correspondingvalues for cycCLSspd and cycCASspd are computed using the slow clockperiod in the denominator so that optimal values are used when the slowclock is employed.

During step 1417, each DRAM device is set to respond to a read operationwith data on the earliest possible clock cycle. For each SPD associatedwith the channel, the value of tDAC is read. This value is converted tocycles according to the formula:cycDACspd=ceiling(tDAC/{Fast Clock period})For each DRAM device associated with this SPD, the following registersare set:tDAC Cycles Fast set to ‘cycDACspd’tCLS Cycles Fast set to ‘cycCLSsys’tCAS Cycles Fast set to ‘cycCASsys’Corresponding values are computed using the slow clock period in thedenominator so that optimal values are used when the slow clock isemployed. A broadcast write is issued with the value 0 to the Read Delayregister of all DRAM devices.

A Fast SCP Frame Cycle indicates the number of cycles that pass betweena PCP that performs a RAS operation and an SCP that performs a CASoperation when the PCP brings a DRAM out of a lower power state into ahigher power state. At step 1418, the Fast and Slow SCP Frame Cycles arecalculated as:(1+tRCD−tCLS).This calculation should use the appropriate values of tRCD and tCLS forfast and slow clock. A broadcast write is performed to all DRAM deviceson the auxiliary channel using these values. This step depends onconfiguring the row parameter cycRCDsys and configuring the columnparameter cycCLSsys.

Operation continues at step 1419, at which the ‘Powerdown Exit Phase 0’and ‘Powerdown Exit Phase 1’ registers are set in preparation forinitial DLL acquisition. The time periods for the first and secondPowerdown exit phases are tPD0 and tPD1, respectively. When a DRAMdevice exits the Powerdown state, the time period that elapses beforethe device should be addressed with commands is based on tPD1. Theperiod tPD0 is the length of time before the DLL of the DRAM devicereaches a predetermined state. For each SPD associated with the channel,the values of tPD0 and tPD1 are read and converted to cycles accordingto the formulas:cycPD0spd=64*ceiling(tPD 0/{powermode SCK period}/64)cycPD1spd=64*ceiling(tPD 1/{powermode SCK period}/64)

The value for cycPDspd is then set as the sum of cycPD0spd andcycPD1spd, and cycPDsys is set as the greatest value of cycPDspd. Foreach DRAM device on the channel, write Powerdown Exit Phase 0 registerto the value of cycPD0/64, derived above the associated SPD value, andwrite Powerdown Exit Phase 1 register to the value of(cycPDsys−cycPD0)/64, using the aggregate value from all SPDs and thevalue for cycPD0 from the SPD associated with this DRAM device. Thisstep precedes any powerdown exit.

At step 1420, a wait is initiated to ensure that the fast clock hassettled to within specifications. Internal registers and pipelines areset to states for proper service operation, at step 1421. The DRAMdevices are instructed to exit the Powerdown state in order for furtherinitialization to be performed, at step 1422. The current is calibrated,at step 1423, for the DRAM devices. A Fast Read Init command isbroadcasted to all DRAM devices on the channel, at step 1424. The devicetemperature compensation circuits are initialized, at step 1425. A waitis initiated to wait for the core timer to expire, at step 1426, toensure that timing constraints are met before core memory operationbegin. Core initialization requirements are satisfied, at step 1427.

Operation continues at step 1428, at which the read domains of the DRAMdevices are levelized. In one embodiment, the main channel supports upto 32 DRAM devices, but the embodiment is not so limited. However,propagation delays on the main channel are such that a device close tothe memory controller responds with data more quickly than a device thatat the most distant point on the main channel. As such, a propagationdelay from the memory controller to at least one of the DRAM devices mayexceed one clock cycle. A memory controller may track the amount of timerequired for each DRAM device to respond with data, but this requires agreat deal of coordination and memory and circuit assets. In oneembodiment, the DRAM devices are levelized, or configured, wherein eachDRAM device will respond to read commands communicated over the mainchannel from the memory controller in the same number of clock cycles.Therefore, levelization is the process by which DRAM device registersare configured so that all DRAM devices respond in the same number ofclock cycles. While levelization is applicable to DRAM devices thatoperate at multiple frequencies, as do the DRAM devices of oneembodiment, the levelization need only be performed once for eachfrequency of operation.

The purpose of levelization is to cause all DRAM devices to respond to aread request in the same number of cycles. This is accomplished bydelaying the read responses of DRAM devices which are nearer the memorycontroller and hence, which could respond more quickly to a read requestthan devices further away from the memory controller since propagationdelays to nearer DRAM devices are shorter. While DRAM devices nearer thememory controller have longer response times than the minimum responsetime, the advantage of levelization is that the memory controller doesnot need to know which DRAM device a read request is directed towards inorder to schedule usage of the wires that form the data bus. Since alllevelized DRAM devices respond in the same number of clock cycles, usageof the wires that form the main channel, or data bus, does not depend onwhich DRAM device data is being read from. If levelization were notperformed, the memory controller would have to schedule data bus usagebased on which DRAM device data was being read from.

In one embodiment, the levelizing comprises determining the responsetime of each of the DRAM devices coupled to the bus using informationcommunicated over at least one bus. Each of the DRAM devices coupled tothe bus may not operate at the same speed, but the embodiment is not solimited. Determining the response time for a DRAM device compriseswriting at least one logic one to at least one memory location of theDRAM device using the bus. Subsequently, a read command is issued overthe bus, wherein the read command is addressed to the at least onememory location of the DRAM device. The memory controller then measuresthe elapsed time between the issuance of the read command and thereceipt of the logic one from the memory location of the. DRAM device,and this elapsed time is the response time of the DRAM device. Theprocess is repeated for each DRAM device coupled to the bus and thememory controller.

Following the determination of a response time for each DRAM devicecoupled to the bus, the individual response times of each of the DRAMdevices are evaluated to determine the longest response time. Using thelongest response time, a delay is computed for each of the DRAM devicescoupled to the bus so that the response time, in clock cycles, of eachof the DRAM devices coupled to the bus equals the longest response time.A delay is programmed in at least one register of each of the DRAMdevices coupled to the bus by writing values to at least one register ofeach of the DRAM devices.

In one embodiment, levelizing comprises the following general steps, butthe embodiment is not so limited:

1. A normalized value of tCLS, cycCLSsys, and tDAC, cycDACspd, has beencomputed to be applicable to all the devices.

2. Write all ones data to the first device on the channel.

3. Determine the round trip delay time from the controller's point ofview of a read to the first device. The round trip delay comprises twoparts: (1) the propagation delay of the read request and read data onthe channel; and, (2) the response time of the first device at thedevice itself. Parameter cycREADrdram is sum of these two times.Parameter cycPROPrdram is the first value and parameter7+cycCLSsys+cycDACspd is the second value.

4. Compute the first value from the round trip delay and the normalizeddevice values of tCLS and tDAC. This value is to be used later on indetermining the minimum offset times between SCP read and write packets.

5. Close the activated row in the first device.

6. Repeat the above steps 2-4 for each device on the channel and collectthe data.

7. Determine the longest round trip delay value from the collected data.Store the value in cycREADsys.

8. For each device on the channel determine how much its round tripdelay differs from the maximum value and store the difference in thedevice, so that it responds in the maximum time.

In one embodiment, programming the delay comprises writing delay valuesto two registers, the read delay register and the tDAC, but theembodiment is not so limited. The delay values of these two registersfor each DRAM device will total to the computed delay for the DRAMdevice. In one embodiment, the tDAC alone is used to control the delaywhen the delay is short enough to be accommodated by the tDAC; if moredelay is needed than can be provided by the tDAC then the fast readdelay register is used to provide additional delay. The SIO signals overthe auxiliary channel are used to communicate the register delay valuesto each of the DRAM devices.

FIG. 15 is a detailed flowchart of the levelization of the DRAM devicesof one embodiment. The following has been performed in previous steps ofthe initialization: cycCLSsys has been set to the same value in all DRAMdevices, as derived from the aggregate of tCLS values; cycDACspd hasbeen set to the minimum possible within each DRAM device from the valueof tDAC in the associated SPD. During the levelization of the DRAMdevices, the following sub-steps are performed for each DRAM device:

a. Perform an Activate on Bank 0, Row 0 to sense Bank 0, Row 0, at step1501.

b. Write and Retire a data packet, with all bits set to 1, to Column 0,at step 1502.

c. Read column 0, at step 1503.

d. Note cycREADrdram as the cycle that returns the first 4 bytes ofdata, as referenced from the beginning of the SCP as cycle 0. Because atthis point the length of time for a DRAM device to respond is not known,the memory controller searches the channel for the first set containinglogical is because this is the data that was written to Bank 0, Row 0,Column 0, at step 1504.

e. At step 1505, a test is made as to whether the DRAM device beinglevelized is the last DRAM device. If the DRAM device being levelized isnot the last DRAM device, operation returns to step 1501. If the DRAMdevice being levelized is the last DRAM device, operation continues atstep 1506, at which the value of the following is noted:cycPROPrdram=cycREADrdram−(7+cycCLSsys+cycDACspd).

f. Precharge Bank 0 and Relax the DRAM device.

g. Based on the values for each DRAM device, cycPROPsys is designated asthe largest cycPROPrdram on the channel, at step 1507.

h. Based on the values from each DRAM device, cycREADsys is assigned asthe largest cycREADrdram on the channel, at step 1508.

i. At step 1509, determine:cycDELAYrdram=(cycREADsys−cycREADrdram).

j. At step 1510, calculate the increase in the tDAC register field tothe largest value it can allow, in order to provide as much of the delayneeded as possible, using:cycDACrdram−max(4,(cycDELAYrdram−cycDACspd)).

k. At step 1511, provide the balance of the delay with the Read Delayregister using:cycDELAYRErdram=cycDELAYrdram−(cycDACrdram−cycDACspd).

l. At step 1512, if the cause of the error is that DRAM devicesrequiring larger tDAC values are at the far end of the channel, thenplacing them closer to the controller corrects the error. Moreover, aslower frequency, if available, could be used to reduce the number ofclock cycles used to create a delay equal to the propagation delay of asignal on the bus. At step 1513, a test is made as to whether the DRAMdevice being levelized is the last DRAM device. If the DRAM device beinglevelized is not the last DRAM device, operation returns to step 1509.If the DRAM device being levelized is the last DRAM device, operationends.

m. Write cycDACrdram to the tDAC Cycles register.

n. Write cycDELAYRErdram to the Read Delay register.

In the initialization of the DRAM devices, a minimum clock cycle offsetis determined between a read command and a subsequent write commandcommunicated to the DRAM devices over the bus. Furthermore, a minimumclock cycle offset is determined between a write command and asubsequent read command communicated to the DRAM devices over the bus.FIG. 16 illustrates the interaction between a Read SCP and a subsequentWrite SCP of one embodiment. FIG. 17 illustrates the interaction betweena Write SCP and a subsequent Read SCP of one embodiment. Both operationsare specified in terms of SCPs, and these figures show how the distancein time between the corresponding data packets changes depending on thedistance between the packets and the master, or memory controller. Bothfigures show time increasing to the left, with the location of thechannel master, a memory controller in one embodiment, placed atlocation x=0, and the location of the last DRAM, or slave, device atlocation x=L. Both figures illustrate the interaction between the SCPsand the corresponding data, resulting in minimum separations betweenRead and Write, and Write and Read, SCPs.

With reference to FIG. 16, Point 1601 illustrates a Read Data packetbeing returned from a DRAM device that is responding to a Read SCP. TheRead Data packet flows down the channel from the right, where the DRAMdevices are located, to the left, where the master is located. Theseparation between the Read SCP and the Read Data, Point 1602, is shownto be equal to the sum of tCAC and tRDLY. The separation between a WriteSCP and the Write Data Packet, Point 1603, is shown to be equal to tCWD.For a Write operation, Write Data flows from the master to the DRAMdevice for which the Write is intended. At the master, it is crucialthat the master does not attempt to send Write data towards the DRAMdevices while a DRAM device is sending Read data back to the master. Toavoid this, the master should wait until the Read Data is completelyreceived before it starts sending Write Data to a DRAM device. Thisresults in the Read and Write Data packets occupying the channel at themaster in back-to-back cycles. In order for this constraint to be met,the following relationship should hold:tCAC+tRDLY+tPACKET=cycRWmin+tPACKET+tCWD,where tPACKET is the length of a packet in cycles. This reduces to:cycRWmin=tCAC+tRDLY−tCWD.

With reference to FIG. 17, Point 1701 illustrates a Write Data packetbeing sent to the DRAM device that is furthest from the master. Point1702 is the Write Data packet being received at the most distant DRAMdevice. Point 1703 is the subsequent Read Data packet being returnedfrom the most distant DRAM device. In this situation, it is importantthat the most distant DRAM device not attempt to return Read Data whileWrite Data is being received. In this case, there should be a one clockcycle separation in time between the Read and Write data at the mostdistant DRAM device. The separation between the Write SCP and the WriteData, Point 1701, is shown to be equal to tCWD. The separation betweenthe Read SCP and the Read Data, Point 1704, is tCAC+tRDLY. To satisfythese constraints, at the master, the separation between a Write SCP anda subsequent Read SCP should obey the relationship:tCWD+tPACKET+cycPROPsys+tCYC=cycWRmin+tPACKET+tCAC+tRDLY,where tPACKET is simply the length of a packet in cycles. This reducesto:cycWRmin=cycPROPsys+tCWD−tCAC−tRDLY+tCYC.As tCYC is one clock cycle, this reduces to:cycWRmin=cycPROPsys+tCWD−tCAC−tRDLY+1.

It should be noted that in the initialization of the DRAM devices, thelevelization step should precede the SCP offset calculation step. Thereason is that important information is collected during thelevelization step that could not otherwise be obtained for the offsetprocess. This information comprises the cycPROPsys parameter, which isdiscovered in the levelization process. In fact even if no levelizationwere to occur, similar calculations would still have to be performed tofind the values of cycPROPsys. Furthermore if levelization had notoccurred, the offset calculation would be different for each device onthe bus. As it happens in one embodiment, the calculation is the sameregardless of which DRAM devices receive the SCPs because all DRAMdevices appear to the memory controller to be in the same physicallocation.

Operation continues at step 1429, at which the minimum offset isdetermined between a read SCP and a subsequent write SCP. A command toperform a read followed by a command to perform a write to the same ordifferent DRAM devices should be separated by some number of channelclock cycles. This offset is determined by column cycle times and isestablished according to the following formula:cycRWmin=tCAC+tRDLY−tCWD.

Operation continues at step 1430, at which the minimum offset isdetermined between a write SCP and a subsequent read SCP. A command toperform a write followed by a command to perform a read to the same ordifferent DRAM devices should be separated by some number of channelcycles. This offset is determined by two factors: turnaroundconstraints, based on propagation delays to the most distant DRAMdevices; and the offset between Read/ Write SCPs as determined at step1429. The offset between Write and Read SCPs is determined according tothe formula:cycWRmin=cycPROPsys+tCWD−tCAC−tRDLY+1.

Refresh requirements for the DRAM device cores are determined, at step1431. At step 1432, the self refresh is configured and enabled for thepower saving modes. The temperature sensor output is configured, at step1433, so it can be enabled or disabled. The fields in each SPD are read,at step 1434, so that the memory controller can establish a powercontrol policy. At step 1435, power modes of the DRAM devices areconfigured according to the desired memory controller policy. Timers arethen started to indicate when Refresh operations need to be performed.The time value for maximum time a device may be in Nap mode is alsoinitialized. Following completion of step 1435, initialization iscomplete.

In operation, each DRAM device of one embodiment may be assigned twoaddresses, wherein the addresses may be provided to registers of theDRAM device over the serial chain, but the embodiment is not so limited.One of the addresses, the device sequence address, is used to addressthe corresponding DRAM device during initialization operations. Theother address, the operating mode address, is used to address thecorresponding DRAM device during memory access operations. The devicesequence addresses may be sequential, but the embodiment is not solimited. The operating mode addresses are determined by the user whenthe memory device array is configured, as it is desirable to assignspecific DRAM devices specific memory locations of the module addressspace.

FIG. 18 is a flowchart of the procedure for setting the device sequenceaddresses in DRAM devices of one embodiment. This procedure wasdiscussed herein with reference to step 1413 of FIG. 14. This flowchartis for a memory array containing 32 DRAM devices, but the embodiment isnot so limited. Operation begins at step 1802, at which the repeaterregister is set to 1 in all of the DRAM devices. The repeater register,when set to 1, is considered to be on and, as such, will place anysignal received on the SIO input pin onto the SIO output pin of the DRAMdevice, thereby propagating the received signal, but the embodiment isnot so limited. The repeater register, when set to 0, is considered tobe off and, as such, will not place the signal received on the SIO inputpin onto the SIO output pin, but the embodiment is not so limited. Atstep 1804, the device sequence address of all DRAM devices is set to bethe highest address used in the device sequence addressing scheme. Forexample, where the array contains 32 DRAM devices and the sequentialaddress scheme uses addresses 0 through 31, the device sequence addressof all DRAM devices is set to 31. If some other address scheme is usedto address the DRAM devices, or if the memory array comprises some othernumber of DRAM devices, the device sequence address set at step 1804would be correspondingly different.

As previously discussed herein, initialization sometimes results inhaving the same commands broadcasted to all DRAM devices of the serialchain. At this point in the device sequence address setting procedure,commands may be broadcasted to all DRAM devices simultaneously becauseall DRAM devices have the same device sequence address and all DRAMdevices have the repeaters on, thereby allowing the command to propagateto all DRAM devices of the auxiliary channel. The remainder of theprocedure is used to set different device sequence addresses in each ofthe DRAM devices of the auxiliary channel.

The repeater register is set to 0 in all of the DRAM devices, at step1806, thereby turning the repeater off. At step 1808, the devicesequence address of the first sequential DRAM device, or the DRAM devicein closest proximity to the memory controller, is set to the addressspecified by the device sequence addressing scheme. For example, ifdevice sequence addresses 0 to 31 are used, the device sequence addressof the DRAM device in closest proximity to the memory controller is setto 0. As the repeater register is off at this point, this devicesequence address is not propagated to other DRAM devices of the serialchain. Furthermore, at step 1808, the device ID counter is incremented.At step 1810, the repeater register of the DRAM device having a devicesequence address set at step 1808 is set to 1. Steps 1808 and 1810 arerepeated for all DRAM devices coupled to the auxiliary channel until allDRAM devices have an assigned device sequence address. As the repeaterregister of the first DRAM device on the auxiliary channel is on, thespecified device sequence address for the second, or next sequential,DRAM device down the auxiliary channel from the memory controller is setwhen step 1808 is repeated. The repeater register is set to 1 in thesecond DRAM device, at step 1810. At step 1812, a determination is madewhether device sequence addresses have been set in all DRAM devices ofthe auxiliary channel. Operation ceases when device sequence addressesare set in all DRAM devices; otherwise, the procedure continues to set adevice sequence address in a DRAM device and turn the repeater on sothat the next serial signal will reach the next DRAM device in sequence.

The invention has been described in conjunction with the preferredembodiment. Although the present invention has been described withreference to specific exemplary embodiments, it will be evident thatvarious modifications and changes may be made to these embodimentswithout departing from the broader spirit and scope of the invention asset forth in the claims. Accordingly, the specification and drawings areto be regarded in an illustrative rather than a restrictive sense.

1-24. (canceled)
 25. A method of operation of a memory device having an array of memory cells, the method comprising: sensing data from the array using a plurality of sense amplifiers; latching a column address that identifies data sensed using the plurality of sense amplifiers; accessing the data, based on the column address, after a first number of clock cycles of a clock signal have elapsed after latching the column address, wherein the first number of clock cycles is represented by a first value stored in a first register on the memory device; and outputting the data after a second number of clock cycles have elapsed after accessing the data, wherein the second number of clock cycles is represented by a second value stored in a second register on the memory device.
 26. The method of claim 25, wherein accessing the data includes a column decoder driving a column select line based on the column address.
 27. The method of claim 26, wherein latching a column address includes latching the column address using the column decoder.
 28. The method of claim 25, further including receiving a row command, wherein sensing data from the array is performed in response to the row command.
 29. The method of claim 25, further including receiving a column command, wherein latching the column address is performed in response to the column command.
 30. The method of claim 29, wherein the column command specifies a read operation.
 31. The method of claim 25, further including: receiving the first value and the second value during an initialization sequence; storing the first value in the first register; and storing the second value in the second register.
 32. The method of claim 25, wherein the first value is determined by dividing a time period of a first timing parameter of the memory device by a period of the clock signal.
 33. The method of claim 25, further including synchronizing outputting the data to the clock signal using a delay lock loop circuit.
 34. The method of claim 25, further including conducting initialization operations at a first frequency of operation; and performing memory access operations at a second frequency of operation, wherein the second frequency is higher than the first frequency.
 35. A method of operation of a memory device having an array of memory cells, the method comprising: sensing data from a row of the array of memory cells using sense amplifiers; accessing data from the sense amplifiers, identified based on a column address, after a first number of clock cycles of a clock signal have elapsed after receiving the column address, wherein the first number of clock cycles is represented by a first value stored in a first register on the memory device; outputting the data after a second number of clock cycles have elapsed after accessing the data from the sense amplifiers, wherein the second number of clock cycles is represented by a second value stored in a second register on the memory device; and synchronizing outputting the data to the clock signal using a delay lock loop circuit.
 36. The method of claim 35, further including activating a wordline of the row of the array of memory cells to sense the data.
 37. The method of claim 35, further including latching the column address in a column decoder after receiving the column address.
 38. The method of claim 37, further including receiving a column command, wherein latching the column address is performed in response to the column command.
 39. The method of claim 38, wherein the column command specifies a read operation.
 40. The method of claim 35, wherein accessing the data includes a column decoder driving a column select line based on the column address.
 41. The method of claim 35, further including receiving a row address, wherein the row address identifies the row of the array of memory cells.
 42. The method of claim 35, further including: receiving the first value and the second value during an initialization sequence; storing the first value in the first register; and storing the second value in the second register.
 43. The method of claim 35, wherein the first value is determined by dividing a time period of a timing parameter of the memory device by a period of the clock signal.
 44. The method of claim 35, further including conducting initialization operations at a first frequency of operation; and performing memory access operations at a second frequency of operation, wherein the second frequency is higher than the first frequency.
 45. A memory device comprising: an array of memory cells; a first register to store a first value; a second register to store a second value; sense amplifiers to sense data from a row of the array of memory cells, wherein data is accessed from the sense amplifiers, identified based on the column address, after a first number of clock cycles of a clock signal have elapsed after receiving the column address, wherein the first number of clock cycles is represented by the first value; and an output driver to output the data after a second number of clock cycles of the clock signal have elapsed after accessing the data from the sense amplifiers, wherein the second number of clock cycles is represented by the second value.
 46. The memory device of claim 45, further including a column decoder to receive the column address.
 47. The memory device of claim 46, further including an interface to receive a column command, wherein the column decoder latches the column address in response to the column command.
 48. The memory device of claim 47, wherein the column command specifies a read operation.
 49. The memory device of claim 45, wherein the first value and the second value are received by the interface during an initialization sequence.
 50. The memory device of claim 45, wherein the first value is determined by dividing a time period of a timing parameter of the memory device by a period of the clock signal.
 51. The memory device of claim 45, further including a delay lock loop circuit, coupled to the output driver, to synchronize the output of the data with the clock signal.
 52. The memory device of claim 51, further including a third register to store a third value, wherein the third value represents of a period of time to elapse before the memory device is ready to receive a column command when recovering from a power down mode, wherein the delay lock loop circuit reacquires synchronization with the clock signal during the period of time.
 53. A memory device comprising: an array of memory cells; a first register to store a first value; a second register to store a second value; a third register to store a third value; sense amplifiers to sense data from a row of the array of memory cells, wherein data is accessed from the sense amplifiers, identified based on the column address, after a first number of clock cycles of a clock signal have elapsed after receiving the column address, wherein the first number of clock cycles is represented by the first value; and an output driver to output the data after a second number of clock cycles of the clock signal have elapsed after accessing the data from the sense amplifiers, wherein the second number of clock cycles is represented by the second value; a delay lock loop circuit, coupled to the output driver, to provide synchronization of the output of the data with the clock signal, wherein synchronization is acquired during a period of time to elapse before the memory device is ready to receive a column command when recovering from a power down mode, wherein the period of time is represented by the third value.
 54. The memory device of claim 53, further including: a column decoder to receive the column address; and an interface to receive a column command, wherein the column decoder latches the column address in response to the column command. 